1. Field of the Invention
The present invention relates to the field of microcode for computer systems, and, more specifically to an apparatus and method for reduction of the address table size required for accessing microcode entries.
2. Description of the Related Art
Many modern day computer systems utilize microcode to generate control signals for the computer systems. Such microcoded systems are described in Wilkes, M. V., The Growth of Interest in Microprogramming: A Literature Survey, Computing Surveys, vol. 1, pp. 139-145, September, 1969.
In general, microcoded computer systems comprise a memory means, such as a read-only memory (ROM), to store microcoded instructions. The microcoded instructions are stored in the memory device with each sequence of microcoded instructions having some defined entry point. A means for determining the entry point of any microcoded sequence corresponding to a given opcode is then provided.
For example, with reference to FIG. 1, a prior art microcoded system is illustrated. In this system, an opcode or macro-instruction is received by a programmed logic array (PLA) circuit 101. The PLA 101 produces, as an output, an entry point address into a microcode sequence memory 102 corresponding to the requested opcode.
The Intel 80386 microprocessor produced by Intel Corporation of Santa Clara, California is an example of such a prior art microcoded computer system.
In such systems, each opcode (macro-instruction) must be mapped by the PLA, or similar device, into an entry point address. As the number of opcodes in a computer system increases, the table size in the look-up device (PLA) becomes large.
It is therefore a primary object of the present invention to develop a system which reduces the table size required for look-up of entry points in a microcoded computer system.